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| PS-AT65609EHW Revision A (R) MICROCIRCUIT, DIGITAL, MEMORY, 8K x 8-Bit, 5V Very Low Power CMOS SRAM, MONOLITHIC SILICON Revision A Written by M. Da Costa / JL Bossis Approved by C. Ferre Date 06/11/2009 1/30 PS-AT65609EHW Rev A DOCUMENTATION CHANGE NOTICE Date 06/11/2009 Revision Change Description A First release 2/30 PS-AT65609EHW Rev A SUMMARY 1 GENERAL ............................................................................................................................................................................5 1.1 1.2 1.3 1.4 1.5 1.6 2 3 SCOPE .............................................................................................................................................................................5 IDENTIFICATION ..............................................................................................................................................................5 ABSOLUTE MAXIMUM RATINGS .......................................................................................................................................5 RECOMMENDED OPERATING CONDITIONS........................................................................................................................5 RADIATION FEATURES .....................................................................................................................................................5 HANDLING PRECAUTIONS ................................................................................................................................................5 APPLICABLE DOCUMENTS ...........................................................................................................................................6 REQUIREMENTS ...............................................................................................................................................................6 3.1 DESIGN, CONSTRUCTION, AND PHYSICAL DIMENSIONS. ...................................................................................................6 3.1.1 Timing waveforms ..................................................................................................................................................6 3.1.2 Package type...........................................................................................................................................................6 3.1.3 Terminal connections .............................................................................................................................................6 3.1.4 Block diagram ........................................................................................................................................................6 3.2 MARKING ........................................................................................................................................................................6 3.2.1 Lead Identification..................................................................................................................................................6 3.2.2 Component Number................................................................................................................................................6 3.2.3 Traceability Information.........................................................................................................................................7 3.3 ELECTRICAL CHARACTERISTICS ......................................................................................................................................7 3.4 BURN-IN TEST .................................................................................................................................................................7 3.4.1 Electrical circuit.....................................................................................................................................................7 3.4.2 Parameters drift value ............................................................................................................................................7 3.5 ENVIRONMENTAL AND ENDURANCE TESTS.....................................................................................................................7 3.5.1 Electrical Circuit for Operating Life Test ..............................................................................................................7 3.5.2 Electrical Measurements at Completion of Environmental and endurance tests ...................................................7 3.5.3 Conditions for Operating Life Test.........................................................................................................................7 3.6 TOTAL DOSE IRRADIATION TESTING ................................................................................................................................7 3.6.1 Bias Conditions ......................................................................................................................................................7 3.6.2 Electrical Measurements ........................................................................................................................................7 4 QUALITY ASSURANCE PROVISIONS ..........................................................................................................................7 4.1 WAFER LOT VALIDATION.................................................................................................................................................7 4.2 SAMPLING AND INSPECTION. ...........................................................................................................................................8 4.3 SCREENING......................................................................................................................................................................8 4.4 QUALITY CONFORMANCE INSPECTION.............................................................................................................................8 4.4.1 Group A inspection.................................................................................................................................................8 4.4.2 Group C inspection.................................................................................................................................................8 4.4.3 Group D inspection. ...............................................................................................................................................8 4.5 DELTA MEASUREMENTS ..................................................................................................................................................8 5 PACKAGING .......................................................................................................................................................................8 5.1 PACKAGING REQUIREMENTS ...........................................................................................................................................8 6 ANNEXES.............................................................................................................................................................................9 6.1 ELECTRICAL AND TIMING CHARACTERISTICS ..................................................................................................................9 6.2 PARAMETER DRIFT VALUES ...........................................................................................................................................18 6.3 TIMING WAVEFORMS .....................................................................................................................................................19 6.3.1 AC Test Conditions:..............................................................................................................................................19 6.3.2 AC Test Loads Waveforms....................................................................................................................................19 6.3.3 Data Retention Mode............................................................................................................................................20 6.3.4 Write cycles ..........................................................................................................................................................21 6.3.5 Read cycles ...........................................................................................................................................................23 6.4 CASE OUTLINE...............................................................................................................................................................24 6.4.1 Package drawing ..................................................................................................................................................24 3/30 PS-AT65609EHW Rev A 6.4.2 Terminal connections ...........................................................................................................................................25 6.5 BLOCK DIAGRAM AND TRUTH TABLE.............................................................................................................................26 6.6 POWER BURN-IN AND OPERATING LIFE TEST ..................................................................................................................27 6.7 TOTAL DOSE RADIATION TEST. ......................................................................................................................................29 FIGURES FIGURE 1 - OUTPUT LOADS .........................................................................................................................................................19 FIGURE 2 - DATA RETENTION TIMING WAVEFORM ......................................................................................................................20 FIGURE 3 - WRITE CYCLE TIMINGS WAVEFORMS.........................................................................................................................21 FIGURE 4 - READ CYCLE TIMINGS WAVEFORMS ..........................................................................................................................23 FIGURE 5 - 28 LEADS DIL SIDE-BRAZED 600 MILS PACKAGE ......................................................................................................24 FIGURE 6 - BLOCK DIAGRAM.......................................................................................................................................................26 FIGURE 7 - ELECTRICAL CIRCUIT FOR BURN-IN AND OPERATING LIFE TEST .................................................................................28 FIGURE 8 - ELECTRICAL CIRCUIT FOR TOTAL DOSE RADIATION TEST...........................................................................................29 TABLES TABLE 1 - ELECTRICAL PERFORMANCES CHARACTERISTICS. .........................................................................................................9 TABLE 2 - WRITE CYCLE TIMING. ...............................................................................................................................................11 TABLE 3 - READ CYCLE TIMING..................................................................................................................................................11 TABLE 4 - PARAMETER DRIFT VALUES ........................................................................................................................................18 TABLE 5 - TERMINAL CONNECTIONS ...........................................................................................................................................25 TABLE 6 - TRUTH TABLE .............................................................................................................................................................26 TABLE 7 - BURN-IN AND LIFE TEST CONDITIONS..........................................................................................................................27 4/30 PS-AT65609EHW Rev A 1 GENERAL 1.1 Scope This specification details the ratings, physical and electrical characteristics, tests and inspection data of the 8K x 8-Bit SRAM named AT65609EHW. It also defines the specific requirement for space and military applications with high reliability. 1.2 Part number Identification Description Access Time 40 ns 40 ns 40 ns Case 28-lead DIL side-brazed 600 Mils 28-lead DIL side-brazed 600 Mils 28-lead DIL side-brazed 600 Mils Level Mil Level B Space Level B Space Level B RHA AT65609EHW-CI40MQ 8K x 8-Bit SRAM AT65609EHW-CI40SV AT65609EHW-CI40SR 8K x 8-Bit SRAM 8K x 8-Bit SRAM 1.3 Absolute maximum ratings Supply voltage range (VCC)................................................. -0.5V to 7.0V DC(*) DC Input voltage range (VIN)............................................... GND-0.3V to VCC + 0.3V(*) DC Output voltage range (VOUT) ........................................ GND-0.3V to VCC + 0.3V(*) Power dissipation (Pd) ....................................................... 0,6 W Storage temperature........................................................... -65C to 150C(*) Maximum junction temperature (TJ).................................... 175C Thermal resistance junction to case (jc) : . ...................... 7C/W Lead temperature (soldering @ 1/16 in, 10 s) ................... 300C NOTE (*) : Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification are not implied. Exposure between recommended DC operating and absolute maximum rating conditions for extended periods may affect device reliability. 1.4 Recommended operating conditions. Supply voltage range (VCC)................................................. 4.5V DC to 5.5V DC Ambient operating temperature (TA) .................................. -55C to 125C Storage temperature........................................................... 30C, 20 to 65% RH, dust free, original packing 1.5 Radiation features Tested up to a Total Dose of .............................................. 300 krads (Si) (according to MIL STD 883 Method 1019) No Single Event Latch-up below a LET Threshold of ........ 80 MeV/mg/cm2 @ 125C 1.6 Handling precautions These components are susceptible to be damaged by electrostatic discharge. Therefore, suitable precautions shall be employed for protection during all phases of manufacturing, testing, shipment and any handling (MIL STD 883 Method 3015.3) ESD (HBM) ........................................................................ > 4000 V ESD (CDM) ........................................................................ > 1000 V 5/30 PS-AT65609EHW Rev A 2 APPLICABLE DOCUMENTS MIL-PRF-38535 ............................................. Integrated Circuits, Manufacturing, General Specification for. MIL-STD-883 ................................................. Test Method Standard Microcircuits. ASTM Standard F1192-95 ............................ Standard guide for the measurement of single event phenomena from heavy ion irradiation of semiconductor devices JEDEC Standard EIA/JESD78 ...................... IC latch-up test ATMEL Aerospace Products Quality Flows In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. 3 REQUIREMENTS 3.1 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein. 3.1.1 Timing waveforms The timing waveforms shall be as specified in Timing waveforms section page 19. 3.1.2 Package type The package shall be a DIL side-brazed 600 Mils, 28 leads as specified in Package drawing section page 24. The case shall be hermetically sealed and have a ceramic body. The leads shall be brazed. 3.1.3 Terminal connections The terminal connections shall be as specified in Terminal connections section page25. 3.1.4 Block diagram The block diagram and the truth table shall be as specified in Block diagram and truth table section page 26. 3.2 Marking Each component shall be marked in respect of: (a) Lead Identification (b) Component Number (c) Traceability Information (d) Manufacturer's Component Number 3.2.1 Lead Identification An index shall be located at the top of the package in the position defined in Package drawing section page 24. 3.2.2 Component Number Each component shall bear the component number which shall be constituted and marked as follows : AT65609EHW - CI 40 SV Product identification Package (CI = 28-lead DIL side-brazed) Speed (40 = 40 ns) Level (MQ=Military Level B, SV=Space Level B, SR=Space Level B RHA) 6/30 PS-AT65609EHW Rev A 3.2.3 Traceability Information Each component shall be marked in respect of traceability information : lot number and date code. 3.3 Electrical characteristics The parameters to be measured with respect of electrical characteristics are scheduled in Electrical and timing characteristics section page 9. The measurements shall be performed at Tamb=22 3C, Thigh=125 (+0/-5)C and Tlow = -55 (+5/-0)C respectively. 3.4 Burn-in test 3.4.1 Electrical circuit Circuit for use in performing the power burn-in is shown in Power burn-in and operating life test section page 27, in accordance with the intent specified in test method 1015 of MIL-STD-883. 3.4.2 Parameters drift value For space level, the parameter drift values applicable to burn-in are specified in Parameter drift values section page 18. Unless otherwise stated, measurements shall be performed at +22 +/- 3C. The parameter drift values (), applicable to the parameters scheduled, shall not be exceeded. In addition to these drift value requirements, the appropriate limit value specified for a given parameter in Electrical and timing characteristics section page 9 shall not be exceeded. . 3.5 Environmental and Endurance Tests 3.5.1 Electrical Circuit for Operating Life Test The circuit for operating life testing shall be as specified for power burn in Power burn-in and operating life test section page 27. 3.5.2 Electrical Measurements at Completion of Environmental and endurance tests The parameters to be measured are scheduled in Electrical and timing characteristics section page 9. Unless otherwise stated, the measurements shall be performed at tamb = 22 +/-3C. 3.5.3 Conditions for Operating Life Test The conditions for operating life testing shall be the same as those specified for power burn in. 3.6 Total dose irradiation testing 3.6.1 Bias Conditions Continuous bias shall be applied during irradiation testing as shown in Total dose radiation test. section page 29. 3.6.2 Electrical Measurements The parameters to be measured prior to, during and on completion of irradiation texture are scheduled in Electrical and timing characteristics section page 9. 4 QUALITY ASSURANCE PROVISIONS 4.1 Wafer lot validation Compliant with ATMEL Quality Management System. For space level, Wafer Lot is accepted by a SEM performed according to AEQC0016 (AEQC0016 referred to MIL-Std-883 method 2018 and 21400 ESCC specification). 7/30 PS-AT65609EHW Rev A 4.2 Sampling and inspection. Sampling and inspection procedures shall be in accordance with MIL-PRF-38535. 4.3 Screening. Screening equivalent to MIL-PRF-38535. Screening shall be conducted on all devices prior to qualification and technology conformance inspection * The burn-in test duration, test condition and test temperature, or approved alternatives shall be as specified in accordance with MIL-PRF-38535. * Additional screening for space application devices shall be as specified in MIL-PRF-38535, appendix B. 4.4 Quality conformance inspection Qualification inspection for high reliability and space level devices shall be in accordance with MIL-PRF38535. Inspections to be performed shall be those specified in MIL-PRF-38535 and herein for groups A, B, C, D, and E inspections. 4.4.1 * * * * * Group A inspection. Tests shall be as specified in Electrical and timing characteristics section page 9. Subgroups 5 and 6 of table I of method 5005 of MIL STD 883 shall be omitted. Subgroups 7 and 8 of table I of method 5005 of MIL STD 883 shall include verifying the functionality of the device. O/V (latch up) tests shall be measured only for the initial qualification and after any process or design changes which may affect the performance of the device. Capacitance measurement shall be measured only for initial qualification and after any process or design changes which may affect input or output capacitance. Capacitance shall be measured between the designated terminal and GND at a frequency of 1 MHz. Sample size is five devices with no failure, and all input and output terminals tested. Group C inspection. 4.4.2 The group C inspection end-point electrical parameters shall be as specified in in Electrical and timing characteristics section page 9. 4.4.3 Group D inspection. The group D inspection end-point electrical parameters shall be as specified in Electrical and timing characteristics section page 9. 4.5 Delta measurements Delta measurements, as specified in Parameter drift values section page 18, shall be made and recorded before and after the required burn-in screens to determine delta compliance. The electrical parameters to be measured, with associated delta limits are listed in Parameter drift values section page 18. The device manufacturer may, at his option, either perform delta measurements or within 24 hours after life test perform final electrical parameter tests, subgroups 1, 7 and 9. 5 PACKAGING 5.1 Packaging requirements The requirements for packaging shall be in accordance with MIL-PRF-38535. 8/30 PS-AT65609EHW Rev A 6 ANNEXES 6.1 Electrical and timing characteristics TABLE 1 - Electrical performances characteristics. Conditions -55C TC +125C +4.5 V Vcc +5.5 V unless otherwise specified Verify truth table Note 1 Verify truth table Note 1 Verify truth table Note 1 Verify truth table Note 1 Iin = -100 A Vcc open, Vss=0 Vcc=5.5V Vin=0V Vcc=5.5V Vin=5.5V Vin( CS 1 ) = 4.5V Limits Min -2 -10 Max -0.2 10 Unit Test Functional test 1 Nominal inputs Functional test 2 Worst case inputs Functional test 3 Worst case outputs Functionnal test 4 Nominal inputs Input clamp voltage to Vss Low level input current High level input current Symbol Test method Mil-Std-883 3014 3014 3014 3014 3008 3009 3010 VIC IIL IIH V A A High impedance output leakage current Third state 1, low level IOZL1 Vin(WE , OE ) = 4.5V Vin(CE) = 0V Vcc=5.5V Vout=0V Vin( CS 1 ) = 0V Vin( WE , OE ) = 4.5V Vin(CE) = 4.5V Vcc=5.5V Vout=0V Vin( CS 1 ) = 4.5V Vin(WE , OE ) = 4.5V Vin(CE) = 0V Vcc=5.5V Vout=5.5V Vin( CS 1 ) = 0V Vin(WE , OE ) =4.5V Vin(CE) = 4.5V Vcc=5.5V Vout=5.5V IOL=8mA Vcc=4.5V Note 2 IOH=-4mA Vcc=4.5V Note 3 -10 - A High impedance output leakage current Third state 2, low level IOZL2 -10 - A High impedance output leakage current Third state 1, high level IOZH1 - - 10 A High impedance output leakage current Third state 2, high level IOZH2 - - 10 A Low level output voltage High level output voltage Standby Supply Current VOL VOH ICCSB 3007 3006 3005 0.4 2.4 5 V V mA CS 1 > VIH or CE< VIL and CS 1 < VIL CS 1 > Vcc-0.3V or CE ICCSB1 3005 3 mA 9/30 PS-AT65609EHW Rev A Conditions -55C TC +125C +4.5 V Vcc +5.5 V unless otherwise specified F=1/TAVAV, Iout=0 mA, WE = OE =Vcc, Vin = GND or Vcc, Vcc max, CS 1 = VIL, CE= VIH, Pattern = ICCACT CS1 = Vcc or CE = CS1 = GND, Vin = GND/Vcc, Vcc = 2V Note 4 Note 5 Note 5 Vin = 0 V TC = 25C fIN = 1.0 MHz Note 9 Vout = 0 V TC = 25C fIN = 1.0 MHz Note 9 Limits Min Max Unit Test Symbol Test method Mil-Std-883 Dynamic Operating Current ICCOP 3005 80 mA Data Retention Current Vcc for data retention Operation Recovery Time Chip deselect to data retention Input capacitance ICCDR1 VCCDR TR TCDR Cin 3005 3012 1.5 2.0 TAVAV 0.0 8 mA V ns ns pF Output capacitance Cout 3012 8 pF 10/30 PS-AT65609EHW Rev A TABLE 2 - Write Cycle Timing. Test method MilStd-883 3003 3003 3003 3003 3003 3003 3003 3003 3003 3003 3003 Conditions -55C TC +125C +4.5 V Vcc +5.5 V unless otherwise specified Vcc = 4.5V & 5.5V Notes 1,6 Vcc = 4.5V & 5.5V Notes 1,6 Vcc = 4.5V Notes 1,6 Vcc = 4.5V Notes 1,7 Vcc = 4.5V Notes 1,6 Vcc = 4.5V Notes 1,6 Vcc = 4.5V & 5.5V Note 8 Vcc = 4.5V Notes 1,7 Vcc = 4.5V & 5.5V Notes 1,6 Vcc = 4.5V & 5.5V Notes 1,7 Vcc = 4.5V & 5.5V Note 8 Limits Min 40 0 35 22 35 35 17 35 3 0 0 Max Unit Symbol Test TAVAW TAVWL TAVWH TDVWH TE1LWH TE2HWH TWLQZ TWLWH TWHAX TWHDX TWHQX Write cycle time Address set-up time Address valid to end of write Data set-up time ns ns ns ns ns ns ns ns ns ns ns CS 1 low to write end CE high to write end Write low to high Z Write pulse width Address hold from to end of write Data hold time Write high to low Z TABLE 3 - Read Cycle Timing. Test method MilStd-883 3003 3003 3003 3003 3003 3003 3003 3003 3003 3003 3003 3003 Conditions -55C TC +125C +4.5 V Vcc +5.5 V unless otherwise specified Vcc = 4.5V & 5.5V Notes 1,6 Vcc = 4.5V & 5.5V Notes 1,7 Vcc = 5.5V Notes 1,6 Vcc = 4.5V Notes 1,7 Vcc = 4.5V & 5.5V Note 8 Vcc = 4.5V & 5.5V Note 8 Vcc = 4.5V Notes 1,7 Vcc = 4.5V & 5.5V Note 8 Vcc = 4.5V & 5.5V Note 8 Vcc = 4.5V Notes 1,7 Vcc = 4.5V & 5.5V Note 8 Vcc = 4.5V & 5.5V Note 8 Limits Min 40 40 3 40 3 15 40 3 15 15 0 10 ns ns ns ns ns ns ns ns ns Max Unit Symbol Test TAVAV TAVQV TAVQX TE1LQV TE1LQX TE1HQZ TE2HQV TE2HQX TE2LQZ TGLQV TGLQX TGHQZ Read cycle time Address access time Address valid to low Z Chip-select1 access time ns ns CS 1 low to low Z CS 1 high to high Z Chip-select2 access time CE high to low Z CE low to high Z Ouput Enable access time OE low to low Z OE high to high Z 11/30 PS-AT65609EHW Rev A NOTES 1) Functional go-no-go test with the following test sequences : FUNCTIONAL TEST 1 Pattern March Checkerboard Imag Genbl Timing (ns) (a,c) 105 105 105 105 VCC (V) 4.5-5.5 4.5-5.5 4.5-5.5 4.5 VSS (V) 0 0 0 0 VIL (V) 0 0 0 0 VIH (V) 3 3 3 3 IOL (mA) 0.5 0.5 0.5 0.5 IOH (mA) -0.5 -0.5 -0.5 -0.5 Vout comp (V) 1.5 1.5 1.5 1.5 FUNCTIONAL TEST 2 Pattern March March March March Timing (ns) (a,c) 105 105 105 105 VCC (V) 6 4 5.5 4.5 VSS (V) 0 0 0 0 VIL (V) -0.3 -0.3 0 0.8 VIH (V) 6.3 4.3 2.2 0 IOL (mA) 0.5 0.5 0.5 0.5 IOH (mA) -0.5 -0.5 -0.5 -0.5 Vout comp (V) 1.5 1.5 1.5 1.5 FUNCTIONAL TEST 3 Pattern March Timing (ns) (a,c) 105 VCC (V) 4.5 VSS (V) 0 VIL (V) 0 VIH (V) 3 IOL (mA) 8 IOH (mA) -4 Vout comp (V) (b) FUNCTIONAL TEST 4 Pattern March Comarch Imag Checkerboard Timing (ns) (a,c) 100 100 100 100 VCC (V) 4.5 and 5.5V 4.5 and 5.5V 4.5 and 5.5V 4.5 and 5.5V VSS (V) 0 0 0 0 VIL (V) 0 0 0 0 VIH (V) 3 3 3 3 IOL (mA) 0.5 0.5 0.5 0.5 IOH (mA) -0.5 -0.5 -0.5 -0.5 Vout comp (V) 1.5 1.5 1.5 1.5 a) a write cycle is followed by a read cycle. The time between start of write and start of read per the truth table is the specified "timing" parameter. tr = tf = 5 ns maximum b) 0.4V for low output level, 2.4V for high output level c) Ouput load 1 TTL gate equivalent + CL < 30 pF 2) Select address inputs to produce a low level at the pin under test. 3) Select address inputs to produce a high level at the pin under test. 4) Measurements are performed with the memory loaded with a background of zeros, then with a background of ones, for all inputs high, then low. Only the worst case is recorded. 12/30 PS-AT65609EHW Rev A 5) Data retention procedure : a) Write memory with CHECKERBOARD pattern b) Power down to VCC = 2V for 250ms c) Restore VCC to 4.5V, wait tr, read memory and compare with original pattern d) Repeat the procedure with CHECKERBOARD pattern 6) Parameter tested go-no-go during functional test 4. 7) Parameter measured during functional test 4 using pattern March at 4.5V and 5.5V. 8) Guaranteed with output loading 5pF but not tested. Characterized at initial design and after major process changes. 9) Guaranteed but not tested 10) The following pattern definitions apply : a) ICCACT Write loop pattern between Nmin and Nmax 13/30 PS-AT65609EHW Rev A b) MARCH Memory size Data Nmin Nmax 8192 1010 1010 0 8191 Write background data N=0 Read and compare Write datab Increment N N YE N > Nmax N = Nmax Read and compare Write datab Decrement N N N<0 YE END 14/30 PS-AT65609EHW Rev A c) Checkerboard Memory size Data Nmin Nmax 8192 1010 1010 0 8191 Write data or datab if Xo = Yo in Nmin Write data or datab if Xo = Yo in N+1 NO N = Nmax YES Read and compare Data or datab if Xo = Yo in Nmin Read and compare Data or datab If Xo = Yo in N+1 NO N = Nmax YES END 15/30 PS-AT65609EHW Rev A d) Imag Write Background Data N=0 N = Nmax Read Cell N Data Read Cell N Datab Write Cell N Datab Write Cell N Data Write Cell N Data Write Cell N Datab Write Cell n Datab Increment N Write Cell N Data Decrement N NO N > Nmax YES Read Cell N Datab Write Cell N Data Write Cell N Datab Increment N N<0 YES Read Cell N Data Write Cell N Datab Write Cell N Data Decrement N NO N > Nmax N<0 YES YES END Memory Size Data Nmax : 8192 : 1010 1010 : 8191 16/30 PS-AT65609EHW Rev A e) Comarch Write Background Data N=0 N=0 Read Cell N Data Read Cell N Data Write Cell N Datab Write Cell N Datab Read Cell Nb Data Read Cell Nb Data Write Cell Nb Datab Write Cell Nb Datab Increment N increment N NO N = Nmax/2 NO N<0 YES N=0 N=0 YES Read cell N Datab Read Cell N Datab Write Cell N Data Write cell N data Read Cell Nb Datab Read Cell Nb Datab Write Cell Nb Data Write Cell Nb Data Increment N Increment N NO NO N > Nmax/2 N = Nmax/2 YES YES END Memory size : 8192 Data : 1010 1010 Nmax : 8191 17/30 PS-AT65609EHW Rev A f) Genbl Write 0 background Write 1 background Read 1 background with OE = VIL Read 1 background with OE = VIH (must be fail) 6.2 Parameter drift values TABLE 4 - Parameter drift values Test Symbol Test method Mil-Std883 As per table 1 As per table 1 As per table 1 As per table 1 As per table 1 As per table 1 As per table 1 Conditions Drift limits Unit Low level Input current High level Input current Output leakage Low current Output leakage High current Stand-by supply current IIL IIH IOZL IOZH ICCSb ICCSb1 Iccdr1 As per table 1 As per table 1 As per table 1 As per table 1 As per table 1 As per table 1 As per table 1 1 1 1 1 0.5 0.3 0.15 A A A A mA mA mA Stand-by supply current Data retention current NOTE: the above parameter shall be recorded before and after burn-in and life test to determine the delta. 18/30 PS-AT65609EHW Rev A 6.3 Timing waveforms 6.3.1 AC Test Conditions: Input Pulse Levels: ....................................................................... GND to 3.0 V Input Rise/Fall Times: ..................................................................................5 ns Input Timing Reference Levels: ................................................................. 1.5V Output Loading IOL/IOH (see Figure 1a and Figure 1b): ........................ 30pF 6.3.2 AC Test Loads Waveforms FIGURE 1 - Output loads 19/30 PS-AT65609EHW Rev A 6.3.3 Data Retention Mode Atmel CMOS RAM's are designed with battery backup in mind. Data retention voltage and supply current are guaranteed over temperature. The following rules ensure data retention: 1. During data retention chip select CS 1 must be held high within VCC to VCC -0.2V or, chip select CE must be held down within GND to GND +0.2V. 2. Output Enable ( OE ) should be held high to keep the RAM outputs high impedance, minimizing power dissipation. 3. During power up and power-down transitions CS 1 and OE must be kept between VCC + 0.3V and 70% of VCC, or with CE between GND and GND -0.3V. 4. The RAM can begin operation > TR ns after VCC reaches the minimum operation voltages (4.5V). FIGURE 2 - Data retention timing waveform 20/30 PS-AT65609EHW Rev A 6.3.4 Write cycles FIGURE 3 - Write cycle timings waveforms Figure 3a - Write Cycle 1 WE controlled, OE High During Write Figure 3b - Write Cycle 2 WE controlled, OE Low 21/30 PS-AT65609EHW Rev A Figure 3c - Write Cycle 3 CS1 or CE controlled NOTE : The internal write time of the memory is defined by the overlap of CS 1 Low and CE HIGH and WE LOW. Both signals must be actived to initiate a write and either signal can terminate a write by going in actived. The data input setup and hold timing should be referenced to the actived edge of the signal that terminates the write. Data out is high impedance if OE = VIH. 22/30 PS-AT65609EHW Rev A 6.3.5 Read cycles FIGURE 4 - Read cycle timings waveforms Figure 4a - Read Cycle 1 Address Controlled ( CS1 = OE Low, CE = WE High) Figure 4b - Read Cycle 2 CS1 Controlled (CE = WE High) Figure 4c - Read Cycle 3 CE Controlled ( WE High, CS1 Low) 23/30 PS-AT65609EHW Rev A 6.4 Case outline 6.4.1 Package drawing FIGURE 5 - 28 leads DIL side-brazed 600 Mils package D 28 15 M LEAD N1 INDEX MARK 14 A2 A A1 H b e D1 e1 (AT STAND OFF) c Ref A A1 A2 b c D D1 e e1 H M Millimeters Min. Nom. 3.73 3.99 1.02 1.27 2.47 2.73 0.41 0.46 0.23 0.25 35.20 35.56 32.89 33.02 2.41 2.54 14.99 15.24 14.86 15.11 Max. Min. 4.24 0.147 1.52 0.040 2.98 0.0974 0.51 0.016 0.30 0.009 35.92 1.386 33.15 1.295 2.67 0.095 15.49 0.590 5.51 15.37 0.585 Inches Nom. Max. 0.157 0.167 0.050 0.060 0.1074 0.1174 0.018 0.020 0.010 0.012 1.400 1.414 1.300 1.305 0.100 0.105 0.600 0.610 0.217 0.595 0.605 24/30 PS-AT65609EHW Rev A 6.4.2 Terminal connections TABLE 5 - Terminal connections Case outline Pin Number 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Description Addresses Chip Enable Chip Select Output Enable Write Enable Data Inputs/Outputs Not connected Power Ground Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Name NC A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND Name A0 - A12 CE CS1 OE Name I/O3 I/O4 I/O5 I/O6 I/O7 CS1 A10 OE A11 A9 A8 CE WE VCC WE I/O0 - I/O7 NC VCC GND 25/30 PS-AT65609EHW Rev A 6.5 Block diagram and truth table FIGURE 6 - Block diagram TABLE 6 - Truth table CS1 CE WE OE X X L X H Inputs/Outputs Mode H X L L L X L H H H X X H L H Z Z Data Out Data In Z Deselect / Power-Down Deselect / Power-Down Read Write Ouput Disable Note: L=low, H=high, X=low or high, Z=high impedance 26/30 PS-AT65609EHW Rev A 6.6 Power burn-in and operating life test TABLE 7 - Burn-in and life test conditions Characteristics Ambient Temperature Address inputs Select pins Control inputs Inputs/Outputs Pulse frequency Positive Supply Voltage Negative Supply Voltage Symbol Tamb Vin CS1 Conditions 125 (+0/-5) S3 to S15 (note 1) Unit C Vac V V Vac Vac kHz V V 0 Vcc S1 and S2 (note 2) S16 and S17 330 +/- 20% 5.7V (+0.1 /-0.1) 0 CE OE , WE Vin S3 VCC GND NOTES : 1 1/ S n = .S n-1 for n>=3 2 2/ Control Input 0us S1 0.3us 0.6us 0.9us 1.2us 1.5us S2 S3 27/30 PS-AT65609EHW Rev A 3/ All Inputs and Outputs shall be connected through a serial protection resistor/load of 1 kOhm as follows : FIGURE 7 - Electrical circuit for burn-in and operating life test 28/30 PS-AT65609EHW Rev A 6.7 Total dose radiation test. FIGURE 8 - Electrical circuit for total dose radiation test. Continuous bias shall be applied during irradiation testing as specified below, through a serial protection resistor/load of 5.6 kOhm. 29/30 PS-AT65609EHW Rev A Headquarters Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 International Atmel Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Product Contact Web Site www.atmel.com Technical Support avr@atmel.com Sales Contact www.atmel.com/contacts Literature Request www.atmel.com/literature Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL'S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL'S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel's products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. (c) 2009 Atmel Corporation. All rights reserved. Atmel(R), logo and combinations thereof, and others, are the registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. 30/30 |
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